(a) Field of the Invention
The present invention relates to a ring oscillator having a variable delay and, more particularly, to a ring oscillator having a variable delay suitably used for a digital phase locked loop (PLL) circuit.
(b) Description of a Related Art
A ring oscillator having a variable delay (delay time) is generally used in a digital PLL circuit as a voltage controlled oscillator (VCO).
A Patent Publication JP-A-6-77782 describes a conventional ring oscillator having a variable delay, wherein the oscillation frequency range and the gain of the ring oscillator can be controlled. The ring oscillator includes a plurality of delay gates cascaded in a ring fashion. The delay gates are provided with a first control block for controlling the oscillation frequency of the delay gates at a coarse delay step by controlling the applied voltage or operational current of the delay gates. A second control bock is also provided for controlling the oscillation frequency of at least one of the delay gates at a fine delay step. By these configurations, the gain control separately from the oscillation frequency is possible in the ring oscillator, whereby fine control for the oscillator frequency can be effected. The second control block has fixed adjustment steps in the fine delay control.
The delay (delay time) of the ring oscillator largely affects the jitter characteristic of the digital PLL circuits, as in the case of the ring oscillator described in the above embodiment. The delay can be generally designed in the ring oscillator by using a simulation. However, it is difficult to compensate variations of delay of the ring oscillator caused by the fabrication process thereof between chips in a wafer or between lots or variations caused by environmental conditions of the ring oscillator. That is, the design for compensation of the variations at least increases the design steps for the ring oscillator, and yet effective compensation for the variations is difficult to achieve in the digital PLL circuit.